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STV9420 stv9421 multisync on-screen display for monitor october 1995 dip20 (plastic package) order code : stv9421 . cmos single chip osd for monitor . built in 1 kbyte ram holding : - pages descriptors - character codes - user definable characters . 128 alphanumeric characters or graphic symbols in internal rom (12 x 18 dot matrix) . up to 26 user definable characters . internal horizontal pll (15 to 120khz) . programmable vertical height of character with a slice interpolator to meet multi-synch requirements . programmable vertical and hori- zontal positioning . flexible screen description . character by character color se- lection (up to 8 different colors) . programmable background (color, transparent or with shadowing) . character blinking . 2-wires asynchronous serial mcu interface (i 2 c protocol) . 4 x 8 bits pwm dac outputs on the stv9421 . single positive 5v supply dip16 (plastic package) order code : STV9420 description the STV9420/21 is an on screen display for monitor. it is built as a slave peripheral connected to a host mcu via a serial i 2 c bus. it includes a display memory, controls all the display attributes and generates pixels from the data read in its on chip memory. the line pll and a special slice interpolator allow to have a display aspect which does not depend on the line and frame frequencies. i 2 c interface allows mcu to make transparent in- ternal access to prepare the next pages during the display of the current page. toggle from one page to another by programming only one register. 4 x 8 bits pwm dac are available (stv9421) to provide dc voltage control to other peripherals. the STV9420/21 provides the user an easy to use and cost effective solution to display alphanumeric or graphic information on monitor screen. 1/16
9420-01.ai / 9421-01.ai pin connections pin description symbol pin number i/o description dip16 dip20 pwm1 1 o dac1 output fblk 1 2 o fast blanking output h-sync 2 3 i horizontal sync input v-sync 3 4 i vertical sync input v dd 4 5 s +5v supply pxck 5 6 o pixel frequency output ckout 6 7 o clock output xtalout 7 8 o crystal output xtalin 8 9 i crystal or clock input pwm4 10 o dac4 output pwm2 11 o dac2 output scl 9 12 i serial clock sda 10 13 i/o serial input/output data reset 11 14 i reset input gnd 12 15 s ground r 13 16 o red output g 14 17 o green output b 15 18 o blue output test 16 19 i reserved (grounded in normal operation) pwm3 20 o dac3 output 9420-01.tbl 1 2 3 4 5 6 7 8 16 test b g r gnd reset sda scl fblk h-sync v-sync v dd pxck ckout xtalout xtalin 15 14 13 12 11 10 9 dip16 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 pwm3 test b g r gnd reset sda scl pwm2 pwm1 fblk h-sync v-sync v dd pxck ckout xtalout xtalin pwm4 dip20 STV9420 - stv9421 2/16
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 ckout hsync vsync reset r g b fblk gnd scl sda xtal in xtal out pxck test v dd address/data STV9420 horizontal digital pll 4k rom (128 characters) 1k ram page descriptors + user defined char. i c bus interface 2 display controller 9420-02.eps block diagrams STV9420 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 pwm pwm3 pwm2 pwm1 pwm4 ckout hsync vsync reset r g b fblk gnd scl sda xtal in xtal out pxck test v dd address/data stv9421 display controller horizontal digital pll 4k rom (128 characters) i c bus interface 2 1k ram page descriptors + user defined char. 9421-02.eps stv9421 STV9420 - stv9421 3/16
absolute maximum ratings symbol parameter value unit v dd supply voltage -0.3, +7.0 v v in input voltage -0.3, +7.0 v t oper operating ambient temperature 0, +70 c t stg storage temperature -40, +125 c 9420-02.tbl electrical characteristics (v dd = 5v, v ss = 0v, t a = 0 to 70c, f xtal = 8 to 15mhz, test = 0 v, unless otherwise specified) symbol parameter min. typ. max. unit supply v dd supply voltage 4.75 5 5.25 v i dd supply current - - 50 ma inputs scl, sda, test, reset, v-sync and h-sync v il input low voltage 0.8 v v ih input high voltage 0.8 v dd v i il input leakage current -20 +20 m a outputs r, g, b, fblk, sda, ckout, pxck and pwmi (i = 1 to 4) v ol output low voltage (i ol = 1.6ma) 0 0.4 v v oh output high voltage (i ol = -0.1ma) 0.8 v dd v dd v 9420-03.tbl for r, g, b and fblk outputs, see figure 1. 5 2.5 0 10 -5 10 -4 10 -3 10 -2 10 -1 i (a) (v) , v ol oh v v ol oh v 9420-17.eps figure 1 : typical r, g, b outputs characteristics STV9420 - stv9421 4/16
timings symbol parameter min. typ. max. unit oscilator input : xti (see figure 2) t wh clock high level 35 ns t wl clock low level 35 ns f xtal clock frequency 6 15 mhz f pxl pixel frequency 30 mhz reset t res reset high level pulse 4 m s r, g, b, fblk (c load = 30pf) t r rise time (note 1) 5 ns t f fall time (note 1) 5 ns t skew skew between r, g, b, fblk (note 1) 5 ns i 2 c interface : sda and scl (see figure 3) f scl scl clock frequency 0 1 mhz t buf time the bus must be free between 2 access 500 ns t hds hold time for start condition 500 ns t sup set up time for stop condition 500 ns t low the low period of clock 400 ns t high the high period of clock 400 ns t hdat hold time data 0 ns t sudat set up time data 375 ns t f fall time of sda 20 ns t r rise time of both scl and sda depend on the pull-up resistor and the load capacitance note 1 : these parameters are not tested on each unit. they are measured during our internal qualification procedure which includes characterization on batches comming from corners of our processes and also temperature characterization. 9420-04.tbl xti t wh t wl 9420-03.eps figure 2 sda t buf scl t hdat stop start data stop t sudat t hds t sup t high t low 9420-04.eps figure 3 STV9420 - stv9421 5/16
functional description the STV9420/21 display processor operation is controlled by a host mcu via the i 2 c interface. it is fully programmable through 8 internal read/write registers (12 for stv9421) and performs all the display functions by generating pixels from data stored in its internal memory. after the page down- loading from the mcu, the STV9420/21 refreshes screen by its built in processor, without any mcu control (access).in addition, the host mcu has a direct access to the on chip 1kbytes ram during the display of the current page to make any update of its contents. with the STV9420/21, a page displayed on the screen is made of several strips which can be of 2 types : spacing or character and which are de- scribed by a table of descriptors and character codes in ram. several pages can be downloaded at the same time in the ram and the choice of the current display page is made by programming the control register. i - serial interface the 2-wires serial interface is an i 2 c interface. to be connected to the i 2 c bus, a device must own its slave address ; the slave address of the STV9420/21 is ba (in hexadecimal). a6 a5 a4 a3 a2 a1 a0 r/w 1011101 i.1 - data transfer in write mode the host mcu can write data into the STV9420/21 registers or ram. to write data into the STV9420/ 21, after a start, the mcu must send (figure 3) : - first, the i 2 c address slave byte with a low level for the r/w bit, - the two bytes of the internal address where the mcu wants to write data(s), - the successive bytes of data(s). all bytes are sent ms bit first and the write data transfer is closed by a stop. i.2 - data transfer in read mode the host mcu can read data from the STV9420/21 registers, ram or rom. to read data from the STV9420/21 (figure 4), the mcu must send 2 different i 2 c sequences. the first one is made of i 2 c slave address byte with r/w bit at low level and the 2 internal address bytes. the second one is made of i 2 c slave address byte with r/w bit at high level and all the successive data bytes read at successive addresses starting from the initial address given by the first sequence. scl sda r/w a7 a6 a5 a4 a3 a2 a1 a0 i 1 c slave address ack lsb address ack msb address ack start - - a13 a12 a10 a10 a9 a8 stop scl sda r/w d7 d6 d5 d4 d3 d2 d1 d0 i 1 c slave address ack ack data byte n ack start d7 d6 d5 d4 d3 d2 d1 d0 stop data byte 1 9420-06.eps figure 4 : STV9420/i 2 c read operation scl sda r/w a7 a6 a5 a4 a3 a2 a1 a0 - - a13 a12 a11 a10 a9 a8 i 2 c slave address ack lsb address ack msb address ack start d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 ack ack data byte 1 data byte 2 ack data byte n stop scl sda 9420-05.ai figure 3 : STV9420/i 2 c write operation STV9420 - stv9421 6/16
functional description (continued) i.3 - addressing space STV9420/21 registers, ram and rom are mapped in a 16kbytes addressing space. the mapping is the following : 0000 descriptors character codes user definable characters 1024 bytes ram 03ff 0400 empty space 1fff 2000 character generator rom 32ff 3300 empty space 3fff 3ff0 internal registers 3fff i.4 - register set line duration 3ff0 - - ld5 ld4 ld3 ld2 ld1 ld0 * - - 111111 ld[5:0] : line duration (number of character period, 1lsb = 12 pixel periods). horizontal delay 3ff1 dd7 dd6 dd5 dd4 dd3 dd2 dd1 dd0 * 00001000 dd[7:0] : horizontal display delay from the h-sync reference falling edge to the 1 st pixel position of the character strips. unit = 3 pixel periods. characters height 3ff2 - - ch5 ch4 ch3 ch2 ch1 ch0 * - - 010010 ch[5:0] : height of the character strips in scan lines. for each scan line, the number of the slice which is displayed is given by : slice-number = round ? ? scan - line - number x 18 ch[5:0] ? ? scan-line-number = number of the current scan line of the strip. display control 3ff3 osd fbk fl1 fl0 - p8 p7 p6 * 0000 - 000 osd : on/off (if 0, r, g, b and fblk are 0). fbk : fast blanking control : = 1 : fblk = 1, forcing black where these is no display, = 0 : fblk is active only during character display. fl[1:0] : flashing mode : - 00 : no flashing. the character attribute is ignored, - 01 : 1/1 flashing (a duty cycle = 50%), - 10 : 1/3 flashing, - 11 : 3/1 flashing. p[8:6] : address of the 1 st descriptor of the current displayed pages. p[13:9] and p[5:0] = 0 ; up to 8 different pages can be stored in the ram. locking condition time constant 3ff4 fr as2 as1 as0 - bs2 bs1 bs0 * 0010 - 010 fr : free running ; if = 1 pll is disabled and the pixel frequency keeps its last value. as[2:0] : ph as e co nst a nt d uri ng l ockin g conditions. bs[2:0] : fr equency constant during locking conditions. capture process time constant 3ff5 - af2 af1 af0 - bf2 bf1 bf0 * - 011 - 011 af[2:0] : phase constant during the capture process. bf[2:0] : frequency constant during the capture process. initial pixel period 3ff6 pp7 pp6 pp5 pp4 pp3 pp2 pp1 pp0 * 00101000 pp[7:0] : value to initialize the pixel period of the pll. frequency multiplier 3ff7 ----fm3fm2fm1fm0 * ---- 1010 fm[3:0] : frequency multiplier of the crystal frequency to reach the high frequency used by the pll to derive the pixel frequency. STV9420 - stv9421 7/16
functional description (continued) the last fourth registers described below are only available with the stv9421 : pulse width modulator 1 3ff8 v17 v16 v15 v14 v13 v12 v11 v10 * 00000000 v1[7:0] : digital value of the 1 st pwm d to a converter (pin1). pulse width modulator 2 3ff9 v27 v26 v25 v24 v23 v22 v21 v20 * 00000000 v2[7:0] : digital value of the 2 d pwm dac (pin11). pulse width modulator 3 3ffa v37 v36 v35 v34 v33 v32 v31 v30 * 00000000 v3[7:0] : digital value of the 3 rd pwm dac (pin20). pulse width modulator 4 3ffb v47 v46 v45 v44 v43 v42 v41 v40 * 00000000 v4[7:0] : digital value of the 4 th pwm dac (pin10). note : * is power on reset value. ii - descriptors spacing msb0------- lsb sl7 sl6 sl5 sl4 sl3 sl2 sl1 sl0 sl[7:0] : the number of the scan lines of the spacing strip (1 to 255). character msb 1 de - zy - - c9 c8 lsb c7 c6 c5 c4 c3 c2 c1 0 c[9:0] : the address of the first character code of the strip (even). de : display enable : - de = 0, r = g = b = 0 and fblk = fbk (display control register) on whole strip, - de = 1, display of the characters. zy : zoom, zy = 1 all the scan lines are repeated once. iii - code format msb set character number lsb bk3 bk2 bk1 bk0 fl rf gf bf fl : flashing attribute (the flashing mode is defined in the display control register). set : the set character number - if set = 0 : rom character, - if set = 1 : if character number is 0 to 25, a user redefinable character (udc) located in ram at the address equal to : 38 x character number, if character number is 26 to 63, space character, if character number >63, end of line. rf, gf, bf : foreground color. bk[3:0] : background : - if bk3 = 0, bk[2:0] = background color r, g and b, - if bk3 = 1, shadowing : bk2 : vertival shadowing, bk1 : horizontal shadowing. (if bk2 = bk1 = 0, the background is transparent). iv - clock and timing the whole timing is derived from the xtalin and the synchro (horizontal and vertival) input fre- quencies. the xtalin input frequency can be an external clock or a crystal signal thanks to xtalin/xtalout pins. the value of this fre- quency can be chosen between 8 and 15mhz, it is available on the ckout pin and is used by the pll to generate a pixel clock locked on the horizontal synchro input signal. iv.1 - horizontal timing the number of pixel periods is given by the line duration register and is equal to : [ld[5:0] + 1 ] x 12 (ld[5:0] : value of the line duration register). this value allows to choose the horizontal size of the characters. the horizontal left margin is given by the hori- zontal delay register and is equal to : [dd[7:0] + 8] x 3 x t pxck (dd[7:0] : value of the display delay register and t pxck : pixel period). this value allows to choose the horizontal position of the characters on the screen. the value of dd[7:0] must be equal or greater than 4 (the mini- mum value of the horizontal delay is 36 x t pxck = 3 character periods). the length of the active area, where r, g, b are different from 0, depends on the number of characters of the strips. STV9420 - stv9421 8/16
h-sync 0 1 2 3 n + 1 n + 2 n + 3 n + 4 ld - 1 ld 0 1 character period r, g, b ld[5:0] fixed dd[7:0] = 4 (min) = 4n + 2 given by number of characters of the strips 9420-07.ai figure 5 : horizontal timing functional description (continued) iv.2 - d to a timing (stv9421) the d to a converters of the stv9421 are pulse width modulater converter. the frequency of the output signal is : f xtal 256 and the duty cycle is : v1[7:0] 256 per cent. after a low pass filter, the average value of the output is : v1 [7:0] 256 v dd 0 1 128 255 v1[7:0] 256 . t xtal pwm1 signal t xtal 9420-08.eps figure 6 : pwm timing v - display control a screen is composed of successive scanlines gath- ered in several strips. each strip is defined by a descriptor stored in memory. a table of descriptors allows screen composition and different tables can be stored in memory at the page addresses (8 possible 1 addresses). two types of strips are available : - spacing strip : its descriptor (see ii) gives the number of black (fbk = 1 in display control register) or transparent (fbk = 0) lines. - character strip : its descriptor gives the memory address of the character codes corresponding to the 1 st displayed character. the characters and attributes (see code format iii) are defined by a succession of codes stored in the ram at ad- dresses starting from the 1 st one given by the descriptor. a character strip can be displayed or not by using the de bit of its descriptor. a zoom can be made on it by using the zy bit. after the falling edge on v-sync, the first strip descriptor is read at the top of the current table of descriptors at the address given by p[8:6] (see display control register) ; if it is a spacing strip, sl[7:0] black or transparent scan lines are displayed ; if it is a character strip, during ch[5:0] x (i + zy) scan lines (ch[5:0] given by the charac- ter height register), the character codes are read at the addresses starting from the 1 st one given by the descriptor until a end of line character or the end of the scan line ; the next descriptor is then read and the same process is repeated until the next falling edge on v-sync. STV9420 - stv9421 9/16
csd fbk fl[1:0] p8 p7 p8 display control register table of the descriptors 2nd character strip codes other table of descriptors other (udc for example) 1st character strip codes 3rd character srtip codes other (codes or descriptors) spacing row1 row2 spacing row3 spacing ram code and descriptors v-sync top spacing strip 1st character strip 2nd character strip 3rd character strip spacing strip | bottom spacing strip screen 9420-09.eps figure 7 : relation between screen/address page/character code in ram slice 18 of the character n?2 only for vertical shadowing (not displayed). 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 123 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 456 36 pixels (= 3 characters) 36 slices (= 2 characters) character number character number on the screen (example for character n?5) in the ram slice 0 slice 1 slice 2 slice 3 slice 4 slice 5 slice 6 slice 7 slice 8 slice 9 slice 10 slice 11 slice 12 slice 13 slice 14 slice 15 slice 16 slice 17 slice 18 : 0x01 : 0x00 : 0x08 : 0x0c : 0x0e : 0x0f : 0x0f : 0x0f : 0x0f : 0x0e : 0x0c : 0x00 : 0x00 : 0x00 : 0x00 : 0x00 : 0x00 : 0x00 : 0x00 0xff = 0xff 0x7f 0x3f 0x1f 0x1f 0x1f 0x1e 0x1e 0x3c 0x3c 0x78 0x78 0xf1 0x00 0x00 0x00 0x00 0x00 odd address even address 9420-10.ai figure 8 : user definable character functional description (continued) STV9420 - stv9421 10/16
01234567 0 1 2 3 c(6:4) c(3:0) character number c(6:0) 4 5 6 7 8 9 a b c d e f 9420-11.eps table 1 : rom character generator functional description (continued) STV9420 - stv9421 11/16
functional description (continued) vi - user definable character the STV9420/21 allows the user to dynamically define character(s) for his own needs (for a special logo for example). like the rom characters, a udc is made of a 12 pixels x 18 slices dot matrix, but one more slice is added for the vertical shad- owing when several udcs are gathered to make a special great character (see figure 8). in a udc, each pixel is defined with a bit, 1 refers to foreground, and 0 to background color. each slice of a udc uses 2 bytes : add + 1 - - - - px11 px10 px9 px8 add (even) px7 px6 px5 px4 px3 px2 px1 px0 px11 is the left most pixel. character slice address : slice address = 38 x (character number) + (slice number). where : - character number is the number given by the character code, - slice number is the number given by the slice interpolator (n of the current slice of the strip : 1 < <18) vii - rom character generator the STV9420/21 includes a rom character gen- erator which is made of 128 alphanumeric or graphic characters (see table 1) viii - pll the pll function of the STV9420/21 provides the internal pixel clock locked on the horizontal synchro signal and used by the display processor to gener- ate the r, g, b and fast blancking signals. it is made of 2 plls. the first one analogic (see figure 9), provides a high frequency signal locked on the crystal frequency. the frequency multiplier is given by : n = 2 (fm[3:0] + 3) where fm[3:0] is the value of the frequency multiplier register. filtre %n f xtal vco n . f xtal 9420-12.ai figure 9 : analogic pll algo %m f h-sync %d m . f h-sync err(n) d(n) n . f xtal 9420-13.ai figure 10 : digital pll the second pll, full digital (see figure 10), pro- vides a pixel frequency locked on the horizontal synchro signal. the ratio between the frequencies of these 2 signals is :m = 12 x (ld[5:0] + 1) where ld[5:0] is the value of the line duration register. viii.1 - programming of the pll registers frequency multiplier (@3ff7) this register gives the ratio between the crystal frequency and the high frequency of the signal used by the 2 nd pll to provide, by division, the pixel clock. the value of this high frequency must be near to 200mhz (for example if the crystal is a 8mhz, the value of fm must be equal to 10) and greater than 6 x (pixel frequency). initial pixel period (@3ff6) this register allows to increase the speed of the convergence of the pll when the horizontal fre- quency changes (new graphic standart). the rela- tionship between fm[3:0], pp[7:0], ld[5:0], f hsync and f xtal is : pp[7:0] = round ? ? 8 2 ( fm[3:0] + 3 ) f xtal 12 ld[5:0] f hsync - 24 ? ? locking condition time constant (@ 3ff4) this register gives the constants as[2:0] and bs[2:0] used by the algo part of the pll (see figure 10) to calculate, from the phase error, err(n), the new value, d(n), of the division of the high fre- quency signal to provide the pixel clock. these two constants are used only in locking condition, which is true, if the phase error is less than a fixed v alue during at least, 4 scan lines. if the phase error becomes greater than the fixed value, the pll is not in locking condition but in capture process. in this case, the algo part of the pll used the other constants, af[2:0] and bf[2:0], given by the next register. capture process time constant (@ 3ff5) the choice between these two time constants (locking condition or capture process) allows to decrease the capture process time by changing the time response of the pll. STV9420 - stv9421 12/16
functional description (continued) viii.2 - how to choose the value of the time constant ? the time response of the pll is given by its char- acteristic equation which is : ( x - 1 ) 2 + (a + b) ( x - 1 ) + b = 0. where : a = 3 ld[5:0] 2 a - 11 and b = 3 ld[5:0] 2 b - 19 . (ld[5:0] = value of the line dura tion register, a = value of the 1st time constant, af or as and b = value of the 2 d time constant, bf or bs). as you can see, the solution depend only on the line duration and the time constants given by the i 2 c registers. if (a + b) 2 - 4 b 3 0 and 2 a - b < 4, the pll is sta- ble and its response is like this presented on figure 11. t pll frequency f 0 f 1 t input frequency f 0 f 1 9420-14.ai figure 11 : time response of the pll/charac- teristic equation solutions (with real solutions) if (a + b) 2 - 4 b 0, the response of the pll is like this presented on figure 12. in this case the pll is stable if t > 0.7 (damping coefficient). t pll frequency f 0 f 1 t input frequency f 0 f 1 9420-115.ai figure 12 : time response of the pll/charac- teristic equation solutions (with complex solutions) the table 2 gives some good values for a and b constants for different values of the line dura- tion. summary for a good working of the pll : - a and b time constants must be chosen among values for which the pll is stable, - b must be equal or greater than a and the differ- ence between them must be less than 3, - the greater (a, b) are, the faster the capture is. an optimal choice for the most of applications might be : - for locking condition : as = 0 and bs = 1, - for capture process : as = 2 and bs = 4. but for each application the time constants can be calculated by solving the characteristic equation and choosing the best response. table 2 : valid time constants examples b \ a0123456 0 yyyy yyyy yyyy yyyn ynnn nnnn nnnn 1 yyyy yyyy yyyy yyyn ynnn nnnn nnnn 2 nyyy yyyy yyyy yyyn ynnn nnnn nnnn 3 nnny yyyy yyyy yyyn ynnn nnnn nnnn 4 nnnn nyyy (1) yyyy yyyn ynnn nnnn nnnn 5 nnnn nnny yyyy yyyn ynnn nnnn nnnn 6 nnnn nnnn nyyy yyyn ynnn nnnn nnnn 7 nnnn nnnn nnny yyyn ynnn nnnn nnnn 9420-05.tbl note : 1. case of a[2:0] = 1 (001) and b[2:0] = 4 (100) : ld 16 32 48 63 valid time constants nyyy value of line duration register (@ 3ff0) : ld = 16 : ld[5:0] = 01 0000 ld = 32 : ld[5:0] = 10 0000 ld = 48 : ld[5:0] = 1 10000 ld = 63 : ld[5:0] = 111111 table meaning : n = no possible capture y = pll can lock STV9420 - stv9421 13/16
osd pwm1 osd pwm2 osd pwm3 osd pwm4 osd hs osd vs osd r osd g osd b osd fblk osd pxck osd b osd g 1 2 3 4 5 6 7 8 9 10 16 17 18 19 20 11 12 13 14 15 q1 12mhz c5 47pf c4 47pf osd pwm4 osd ckout osd pxck osd vs osd hs osd pwm1 osd fblk c3 100nf v cc r7 2.2k w osd pwm2 osd scl osd sda osd r osd pwm3 s1 v cc reset button v cc r3 2.2k w r4 2.2k w v cc 4 3 2 1 j1 i c 2 1 6 11 2 7 12 3 8 13 4 9 14 5 10 15 vga1 r vga1 g vga1 b j2 to pc 1 6 11 2 7 12 3 8 13 4 9 14 5 10 15 vga2 r vga2 g vga2 b j3 pc mon 1 6 11 2 7 12 3 8 13 4 9 14 5 10 15 vga3 r vga3 g vga3 b j4 appl mon v-sync r1 1k w c1 10 m f 4 5 6 12 13 11 osd vs r6 1k w r5 1k w h-sync r2 1k w c2 10 m f 1 2 3 9 10 8 osd hs v cc u2a 74hc86 u2c 74hc86 u2d 74hc86 u2b 74hc86 c7 470 m f c6 100nf j5 j6 5v power supply v cc osd ckout tp1 tp2 tp3 tp4 tp5 tp6 tp7 tp8 tp9 tp10 tp11 tp12 tp13 tp14 tp15 v cc bc547b t1 r17 10 w r8 82 w r9 75 w r10 3.3k w r22 1.8k w d1 1n4148 s2 bc547b t3 r19 10 w r14 82 w r15 75 w r16 3.3k w r20 1.8k w d3 1n4148 s4 bc547b t2 r18 10 w r11 82 w r12 75 w r13 3.3k w r21 1.8k w d2 1n4148 s3 vga1 r vga1 g vga1 b vga2 r vga2 g vga2 b vga3 r vga3 g vga3 b osd b osd g osd r s t v 9 4 2 1 9420-16.eps a demonstration board is available through your usual sgs-thomson sales office. this demonstration board alllows to test very easily the STV9420/21 performances on any personnal computer. the board is delive red together with a "page maker" software which allows to eas ily generate pages of text or graphics on the pc monitor, or on a second monitor. the i 2 c sequences are generated by the pc parallel port and send to the demobaord through an i 2 c interface which is also delivered together with demoboard. of course, a small manual is also inside the kit. demo kit STV9420 - stv9421 14/16
pm-dip16.wmf package mechanical data (STV9420) 16 pins - plastic dip dimensions millimeters inches min. typ. max. min. typ. max. a1 0.51 0.020 b 0.77 1.65 0.030 0.065 b 0.5 0.020 b1 0.25 0.010 d 20 0.787 e 8.5 0.335 e 2.54 0.100 e3 17.78 0.700 f 7.1 0.280 i 5.1 0.201 l 3.3 0.130 z 1.27 0.050 dip16.tbl STV9420 - stv9421 15/16
pm-dip20.eps package mechanical data (stv9421) 20 pins - plastic dip dimensions millimeters inches min. typ. max. min. typ. max. a1 0.254 0.010 b 1.39 1.65 0.055 0.065 b 0.45 0.018 b1 0.25 0.010 d 25.4 1.000 e 8.5 0.335 e 2.54 0.100 e3 22.86 0.900 f 7.1 0.280 i 3.93 0.155 l 3.3 0.130 z 1.34 0.053 dip20.tbl information furnished is believed to be accurate and reliable. however, sgs-thomson microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no licence is granted by implication or otherwise under any patent or patent rights of sgs-thomson microelectroni cs. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. sgs-thomson microelectronics products are not authorized for use as critical components in lif e support devices or systems without express written approval of sgs-thomson microelectronics. ? 1995 sgs-thomson microelectronics - all rights reserved purchase of i 2 c components of sgs-thomson microelectronics, conveys a license under the philips i 2 c patent. rights to use these components in a i 2 c system, is granted provided that the system conforms to the i 2 c standard specifications as defined by philips. sgs-thomson microelectronics group of companies australia - brazil - china - france - germany - hong kong - i taly - japan - korea - malaysia - malta - morocco the netherlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. STV9420 - stv9421 16/16

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